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timing-diagram

siggi creates a signal diagram from text

Rust
4
4 年前

In this repository, I will be posting contents to learn about UML diagrams and practical examples for all the UML diagrams which I have designed using Lucid Charts

4
4 年前

This repository is basic start of building your own processor using verilog (hdl).

Verilog
0
8 年前

logi.js is a JavaScript library for working with Boolean algebra, logical expressions, truth tables, the Quine-McCluskey algorithm, timing diagrams, and more.

TypeScript
0
2 年前

Design a 4-bit ALU capable of performing 4 different arithmetic or logical operations using Quartus, implement it using Verilog HDL, and verify it using a timing diagram.

0
3 个月前