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Verilog

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Wikipedia: 维基百科

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

logisim-evolution 教学 circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl Verilog

Java

6257

788

2 天前

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga xilinx Verilog pynq

5006

761

3 年前

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

chisel chisel3 Scala firrtl rtl chip-generator Verilog

Scala

4424

639

9 小时前

open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

fpga ofdm 802-11 zynq Linux xilinx analog-devices mac80211 csma dma Verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware

4352

728

11 天前

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

Verilog system-verilog verilog-simulator verilator compilers C++systemc rtl

C++

3091

706

1 天前

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V soc cpu vhdl Verilog fpga

Assembly

2890

468

3 个月前

SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RISC-V cpu core china Verilog nuclei

Verilog

2769

1041

5 年前

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V Verilog fpga core

Verilog

2418

317

3 个月前

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opendb-database openroad lef Verilog timing-analysis def eda rtl gdsii C++tcl

Verilog

2195

718

17 小时前

jbush001 / NyuziProcessor

GPGPU microprocessor architecture

fpga gpu-computing gpu Verilog hardware microprocessor graphics processor-architecture

2124

362

1 年前

cocotb / cocotb

cocotb: Python-based chip (RTL) verification

Python vhdl Verilog verification Testing

Python

2102

580

1 天前

SpinalHDL / SpinalHDL

Scala based HDL

Scala rtl vhdl Verilog fpga

Scala

1855

363

4 天前

pConst / basic_verilog

Must-have verilog systemverilog modules

fpga delay debounce encoder xilinx Verilog tcl synchronizer pwm uart hls

Verilog

1848

410

2 个月前

FPGAwars / icestudio

❄ Visual editor for open FPGA boards

editor fpga blocks Verilog ide JavaScript

JavaScript

1822

262

2 个月前

analogdevicesinc / hdl

HDL libraries and projects

analog-devices Verilog fpga Hacktoberfest

Verilog

1749

1600

2 天前

olofk / serv

SERV - The SErial RISC-V CPU

Verilog fpga asic RISC-V

Verilog

1655

229

9 天前

riscv-mcu / e203_hbirdv2

The Ultra-Low Power RISC-V Core

RISC-V fpga hummingbird nuclei soc china Verilog cpu core

Verilog

1617

390

2 个月前

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python

1596

402

19 天前