rtl

Chisel: A Modern Hardware Design Language

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL

Rocket Chip Generator

Verilator open-source SystemVerilog simulator and lint system

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

Scala based HDL

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Modular hardware build system

A simple yet powerful JQuery star rating plugin with fractional rating support.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

Various HDL (Verilog) IP Cores

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

Veryl: A Modern Hardware Description Language