verilog-simulator

Verilator open-source SystemVerilog simulator and lint system

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

5-stage pipelined 32-bit MIPS microprocessor in Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

A place to keep my synthesizable verilog examples.

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

Verilog HDL Parser

A playground based on the classic version of the Cloud V IDE

32-bits MIPS Processor with 5-stage pipeline

Digital System Design Verilog Implementation

Computer Architecture Lab Course 2022/1400, Fall CSE & IT Dept., Shiraz University

A verilog program that mimics the circuitry of a 4-bit register implemented with four 4x1 multiplexers and four D-Flipflops

"Repository containing a collection of Verilog code modules and test bench for digital design projects. "

This Repository shows the implementation and results of various codes that I write in Verilog HDL

32-bit MIPS processor fully supporting all core instructions