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gtkwave

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buserror / simavr

simavr is a lean, mean and hackable AVR simulator for linux & OSX

simavr avr-gcc gtkwave C avr-simulator embedded debugger

C

1673

386

3 个月前

VCD file (Value Change Dump) command line viewer

vhdl gtkwave 命令行界面

C

119

12

3 年前

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Verilog systemverilog Test-driven development tdd-utilities Python simulator flow gtkwave foss testcase mit-license Simulation verilator

Python

80

17

10 个月前

tscheipel / HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

c-programming computer-architecture gtkwave pipelines processor-architecture RISC-V rv32i system-verilog systemverilog verilator

SystemVerilog

79

7

2 个月前

IBM / hdl-tools

Facilitates building open source tools for working with hardware description languages (HDLs)

rtl Verilog verilator gtkwave

Perl

64

12

6 年前

JeffDeCola / my-verilog-examples

A place to keep my synthesizable verilog examples.

systemverilog gtkwave Verilog hardware fpga asic verilog-simulator simulator waveform xilinx synthesis

Verilog

42

11

4 个月前

albertxie / iverilog-tutorial

Quickstart guide on Icarus Verilog.

gtkwave signal Verilog

Verilog

41

11

5 年前

Scripts to build and use docker images including GHDL

dockerfiles Simulation vhdl hardware 持续集成 gtkwave Actions yosys synthesis Verilog

Shell

41

11

9 个月前

maazm007 / vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

RISC-V gcc-complier gtkwave yosys

C

30

15

1 个月前

arhamhashmi01 / rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

computer-architecture gtkwave hardware-designs microprocessor RISC-V Verilog vhdl vlsi rv32i verilator rv32im

Verilog

15

0

6 个月前

Elphel / vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

Verilog eclipse ide gtkwave

Java

15

1

8 年前

machitgarha / parvaj

Easy and fast VHDL simulation tool, integrating GHDL and GTKWave

vhdl gtkwave console-application build Testing Simulation automated

PHP

14

2

1 年前

umarcor / SIEAV

Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

octave MATLAB gtkwave

VHDL

13

6

6 天前

TheOneKevin / icarusext

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

Verilog gtkwave VS Code Extension

TypeScript

11

3

2 年前

cclienti / wavedisp

Python classes to create agnostic wave files for HDL simulator viewer

vhdl Verilog gtkwave Python

Python

11

1

5 年前

SinaKarvandi / hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic chisel chisel3 fpga gtkwave openram verilator Verilog vhdl vitis vivado-hls

VHDL

9

2

2 年前

five-embeddev / riscv-gtkwave

GTKWave Decoders for RISCV

dissassembler elf-parser gtkwave RISC-V

C++

9

0

4 天前

bluecmd / fst-example

Example how to use the Fast Signal Trace (FST) format and library

C

9

1

5 年前

Alfredosavi / tangnano-hello

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

Docker fpga hello-world sipeed yosys makefile Open Source blink gtkwave icarus

Makefile

8

1

1 年前

agoessling / rules_verilog

Utilities for working with Verilog within Bazel.

Verilog bazel gtkwave bazel-rules fpga

Python

8

1

5 年前