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Verilator open-source SystemVerilog simulator and lint system
Control and Status Register map generator for HDL projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
Connecting FPGA and Arduino using SPI.
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.
My solutions for Bilkent University CS224 Computer Organization Labs (Spring 2019). Includes assembly programming assignments together with various processor designs in System Verilog HDL
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
Example of Python and PyTest powered workflow for a HDL simulation
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
16 bit serial multiplier in SystemVerilog
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
Spice to Verilog Converter
An abstract language model of SystemVerilog (incl. Verilog) written in Python.
Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog