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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python

1466

394

2 个月前

limbo018 / DREAMPlace

Deep learning toolkit-enabled VLSI placement

深度学习 PyTorch vlsi gpu-acceleration

C++

782

216

4 天前

OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

vlsi C++parallel-computing Verilog eda cad

Verilog

609

153

2 年前

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

vhdl poc-library Python Simulation synthesis verification vlsi fpga hardware-designs asic xilinx regression-testing

VHDL

577

103

4 年前

efabless / openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

asic eda gdsii lvs openroad pdk silicon Verilog vlsi flow

Python

280

2 个月前

DegateCommunity / Degate

A modern and open-source cross-platform software for chips reverse engineering.

Verilog vlsi vhdl GUI 逆向工程安全 Cybersecurity multi-platform chips C++cross-platform

C++

259

5 个月前

arm-university / VLSI-Fundamentals-Education-Kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

microprocessor-implementation cadence-virtuoso synopsys-design arm computer-engineering electrical-engineering hardware-designs vlsi devices-circuits-materials

HTML

237

9 个月前