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openram

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google / skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

eda openroad openram asic asic-library skywater pdk magic

Python

3232

425

10 个月前

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python

1558

402

1 个月前

efabless / caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys openroad openram

Verilog

344

6 个月前

efabless / caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic openram openroad yosys

Verilog

137

140

3 年前

ShonTaware / SRAM_SKY130

Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

openram

SourcePawn

4 年前

SinaKarvandi / hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic chisel chisel3 fpga gtkwave openram verilator Verilog vhdl vitis vivado-hls

VHDL

2 年前