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skywater

google/skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Python
3116
6 个月前

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Python
1467
2 个月前

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Verilog
153
3 年前

Index of the fully open source process design kits (PDKs) maintained by Google.

92
3 年前

SKY130 ReRAM and examples (SkyWater Provided)

38
3 年前

Fully-differential asynchronous non-binary 12-bit SAR-ADC

Verilog
31
2 年前

Minimal SKY130 example with self-checking LVS, DRC, and PEX

Shell
23
4 年前

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

Tcl
23
2 年前

GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk

Python
13
4 年前

PLL configuration generator for the Caravel management core

Python
10
4 年前

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Verilog
10
1 年前

SRAM build space for SKY90FD provided by SkyWater.

9
3 年前

Primitives for SKY90FD provided by SkyWater.

6
3 年前

Standard cells for SKY90FD provided by SkyWater.

5
3 年前

Standard cells for SKY90FD provided by Oklahoma State University.

4
3 年前

IO and periphery cells for SKY90FD provided by SkyWater.

4
3 年前

SKY130 spice simulation playground

PostScript
2
4 年前

Full Ubuntu setup for Analog and Digital design

Shell
1
3 年前

skywater-pdk builder

Shell
1
3 年前