verilator

Verilator open-source SystemVerilog simulator and lint system

RISC-V CPU Core (RV32IM)

A small, light weight, RISC CPU soft core

32-bit Superscalar RISC-V CPU

VeeR EH1 core

Various HDL (Verilog) IP Cores

An abstraction library for interfacing EDA tools

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

HDL support for VS Code

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

A simple, basic, formally verified UART controller

VeeR EL2 Core

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

A configurable C++ generator of pipelined Verilog FFT cores

A utility for Composing FPGA designs from Peripherals

A Video display simulator

An Open Source configuration of the Arty platform

A collection of phase locked loop (PLL) related projects

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.