branch-prediction

32-bit Superscalar RISC-V CPU

Go library providing algorithms optimized to leverage the characteristics of modern CPUs

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

Advanced Architecture Labs with CVA6

Super scalar Processor design

🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.

Kite: Architecture Simulator for RISC-V Instruction Set

Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor

Computer Architecture UIUC SP 2018

A branch predictor simulator in C++ that tests 6 different types of branch predictors.

A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog

Computer architecture related projects

Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4

VHDL code of three branch predictors

Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.

System benchmarks over JVM with JMH - SIMD (superscalar processing), Branch prediction, False sharing.

A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.

2 bit saturated branch predictor with BHR (Branch History Register)

Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.