rv32im

RISC-V CPU Core (RV32IM)

A self-hosting and educational C optimizing compiler

32-bit Superscalar RISC-V CPU

Simple 3-stage pipeline RISC-V processor

Trivial RISC-V Linux binary bootloader

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.

miniSpartan6+ (Spartan6) FPGA based MP3 Player

Some materials and sample source for RV32 OS projects.

A web-based RISC-V simulator https://riscv-simulator-five.vercel.app

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

RISC-V ISA emulator

The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbb Zbs Sdext Sdtrig microcontroller

RV32IM System-on-Chip (SoC)

A synthesizable RISC-V RV32IM microcontroller written in VHDL

Becoming acquainted with the RISC-V ISA by writing an emulator

Verilog-based single-cycle CPU implementing the RV32IM instruction set. Supports integer and multiplication/division instructions with modular design, ALU, control unit, and UART-based debugging.

RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards

Softcore microcontroller with peripherals based on PicoRV32