chisel

Open-source high-performance RISC-V processor

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

SonicBOOM: The Berkeley Out-of-Order Machine

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Simple RISC-V 3-stage Pipeline in Chisel

Work in progress prototype for the Chisel Level Editor, for Unity

A .NET XOR encrypted cobalt strike aggressor implementation for chisel to utilize faster proxy and advanced socks5 capabilities.

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

All-in-one OPIran scripts

Establish a Reverse Tunnel between different servers and clients. IPV4 | IPV6 - Supports TCP & UDP . You can establish a tunnel between 5 Kharej servers & 1 IRAN server and vice versa.

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

The batteries-included testing and formal verification library for Chisel-based RTL designs.

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

A compact guide to network pivoting for penetration testings / CTF challenges.

A Chisel RTL generator for network-on-chip interconnects

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

high-performance RTL simulator

Support files for participating in a Fomu workshop

A dynamic verification library for Chisel.