rocket-chip

Rocket Chip Generator

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

SonicBOOM: The Berkeley Out-of-Order Machine

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards

Tests for example Rocket Custom Coprocessors

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

A fault-injection framework using Chisel and FIRRTL

Run Rocket Chip on VCU128

Network components (NIC, Switch) for FireBox

BOOM's Simulation Accelerator.

A simple baremetal program template for RISC-V inspired from riscv benchmark tests

Parallella RISC-V Prebuilt Images

😱 RoCC Accelerator Integration with Chipyard

Annotate rocket-chip