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chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Scala
1985
1 天前

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

Python
86
2 天前

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

C
65
3 年前

Unified open-source repository for OmniXtend protocol implementations in C, Verilog, and Chisel, supporting host and memory roles.

Lua
13
1 个月前

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

Verilog
9
4 年前

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

Verilog
9
5 年前

An online viewer for Chipyard output files

TypeScript
6
4 年前

This Github repository serves as a User Guide (UG) for new Chipyard users.

Python
1
1 年前