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Verilog

Website
Wikipedia: 维基百科

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

langhuihui / monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

livestream mediaserver hls WebRTC rtmp rtsp Verilog WebSocket flv rtp ts mp4 record relay srt webtransport

2178

315

1 天前

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RISC-V vhdl fpga soc Microcontroller processor cpu system-on-chip embedded rtos smp multi-core Verilog

VHDL

1871

281

6 小时前

amaranth-lang / amaranth

A modern hardware definition language and toolchain based on Python

fpga Verilog

Python

1806

182

1 个月前

analogdevicesinc / hdl

HDL libraries and projects

analog-devices Verilog fpga Hacktoberfest

Verilog

1747

1602

1 天前

aappleby / metroboy

A repository of gate-level simulators and tools for the original Game Boy.

Verilog Game Boy gameboy-emulator simulator 模拟器

C++

1151

7 个月前

drom / awesome-hdl

Hardware Description Languages

Awesome Lists Verilog vhdl Hacktoberfest

1068

101

3 个月前

veryl-lang / veryl

Veryl: A Modern Hardware Description Language

rtl Rust systemverilog Verilog

Rust

799

2 天前

m-labs / nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fpga Verilog yosys nmigen

Python

679

4 年前

WangXuan95 / BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

fpga Verilog

Bluespec

588

2 年前

intel / rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

hardware verification Verilog simulator 框架 hardware-design rtl

Dart

445

4 天前

Nuand / bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

bladerf vhdl Verilog rtl ofdm

VHDL

436

1 年前

pymtl / pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Python Verilog systemverilog open-source-hardware rtl

Python

431

1 个月前

slaclab / surf

A huge VHDL library for FPGA and digital ASIC development

asic firmware fpga Verilog Python vhdl

VHDL

401

1 天前

analogdevicesinc / plutosdr-fw

PlutoSDR Firmware

plutosdr sdr iio fpga Verilog Linux Robot Framework

Shell

398

221

1 年前

tensil-ai / tensil

Open source machine learning accelerators

机器学习 silicon fpga 人工智能 asic Verilog Scala

Scala

388

2 年前

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog verification synthesis fpga asic cdc verilator async

Verilog

382

19 天前

viduraakalanka / HDL-Bits-Solutions

This is a repository containing solutions to the problem statements given in HDL Bits website.

Verilog

363

101

2 年前

chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

systemverilog Verilog rtl

SystemVerilog

344

1 天前

spamegg1 / reviews

Reviewing some online CS courses I took

编程语言算法 computer-graphics 数据库 logic 数学 Network 操作系统 Assembly Verilog Java JavaScript Python Racket Ruby Scala Kotlin C

JavaScript

332

7 个月前

Kitware / VeloView

VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.

lidar Verilog velodyne sensor-data

C++

323

165

4 年前