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open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

fpga ofdm 802-11 zynq Linux xilinx analog-devices mac80211 csma dma Verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware

4119

697

2 天前

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

fpga ofdm wi-fi zynq Linux mac80211 csma dma Verilog hls xilinx analog-devices ad9361 sdr software-defined-radio ieee80211 hardware vhdl rtl

Verilog

746

255

2 天前

MeowLucian / SDR_Matlab_OFDM_802.11a

📡 Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz

MATLAB ad9361 ofdm zynq xilinx sdr hardware radio GUI packets

MATLAB

178

7 年前

analogdevicesinc / gr-iio

IIO blocks for GNU Radio

gnuradio iio plutosdr ad9361

C++

100

2 年前

MeowLucian / SDR_Matlab_OFDM_802.11n

📡 Using Software Designed Radio to transmit MIMO-OFDM QPSK signals at 5 GHz

MATLAB ad9361 ofdm ieee80211 zynq xilinx analog-devices sdr hardware GUI radio

MATLAB

7 年前

analogdevicesinc / libad9361-iio

IIO AD9361 library for filter design and handling, multi-chip sync, etc.

iio ad9361 fir plutosdr Hacktoberfest

5 个月前

Grootzz / AD9361_TX_MSK

A project demonstrate how to config ad9361 to TX mode and how to transmit MSK

Verilog ad9361 fpga

Verilog

6 年前

analogdevicesinc / ad936x-filter-wizard

MATLAB-based FIR filter design

ad9361 MATLAB

MATLAB

7 个月前

MeowLucian / SDR_FM_Radio

📻 Using Software Designed Radio to transmit & receive FM signal

ad9361 zynq xilinx analog-devices fm radio station demodulation sdr

MATLAB

7 年前

MeowLucian / SDR_Matlab_LTE

📡 Using Software Designed Radio to transmit LTE downlink signals at 2.4 GHz

MATLAB ad9361 ofdm zynq xilinx analog-devices sdr hardware radio GUI software-defined-radio iio

MATLAB

6 年前

MeowLucian / SDR_Matlab_OFDM_802.11a_16QAM

📡 Using Software Designed Radio to transmit OFDM 16QAM signals at 5 GHz

MATLAB ad9361 offline ieee80211 zynq xilinx analog-devices sdr hardware radio packets GUI ofdm

MATLAB

7 年前

vankxr / icyradio

Over-engineered SDR development board

fpga sdr software-defined-radio ice40 ad9361 artix-7 cm4 hardware Verilog mmwave usb-pd

VHDL

5 个月前

Grootzz / AD9361_TX_GMSK

A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK

Verilog ad9361

VHDL

6 年前

Grootzz / AD9361_TX_1MHz_Baseband_800Hz_IF

A project demonstrate how to config ad9361 to TX mode

Verilog ad9361

VHDL

6 年前

rodrigo455 / AD936X_LIBIIO

REDHAWK FrontEnd Interface for the transceivers AD9361, AD9364, AD9363

ad9361 plutosdr iio sdr

C++

7 年前

briansune / MLK-L1-CZ06-DR1M90G-FM-Radio

MLK-L1-CZ06-DR1M90G FM Radio

ad9361 fpga Verilog

Verilog

4 个月前

ddurfeeEngineer / ad9361-iiostream-loopback

example of using iio to stream data from AD9361 with a coax cable loopback

ad9361 sdr vitis xilinx zed iio analog-devices zynq

1 年前

Bucknalla / AD9361_ZyCAP

PL Layer Controls for the AD9361 RF Front End

ad9361 xilinx-fpga

7 年前