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cts

JavaScript
27
2 个月前

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

Verilog
12
1 年前

Control Frame Attack Vulnerability Detection Tool (GitLab Mirror)

C
10
10 个月前

Utility that allows the display of any image cropped from an external image file (Bitmap images of type jpeg,png and bmp) into any sized image on the screen in any coordinate available to the display system.

C#
10
3 年前

symmetric clock tree synthesis for NTV IC design

Python
10
3 年前

Interfacing to BCMS CTS

Python
8
10 个月前

An installer designed to help you install the combat tests.

Java
6
1 年前

The ultimate enhancement for displaying of transport requests in SAP GUI

ABAP
4
4 个月前

A repository containing mods that are compatible with the combat test snapshot 8c.

4
1 年前

AES CBC Ciphertext Stealing mode for Go

Go
3
6 年前

This repository presents a complete RTL-to-GDSII ASIC implementation of the PicoRV32 RISC-V processor using the Skywater 130nm (Sky130) open-source PDK. The project demonstrates an industry-standard VLSI backend flow using Cadence EDA tools, covering synthesis, placement, routing, verification, and GDSII generation.

Verilog
3
20 天前

For the Cognizant Early Engagement Program [Continuous Skill Development], look for solutions.

2
7 个月前

Dumps of kernel sources from the conformance test runs residing in OpenCL-CTS repo

C
2
4 年前

RSS Feeds for various NPCI Circulars and Notifications.

Python
2
1 个月前

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

Verilog
2
2 年前