high-level-synthesis

XLS: Accelerated HW Synthesis

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

DaCe - Data Centric Parallel Programming

Intermediate Language (IL) for Hardware Accelerator Generators

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

FPGA Accelerator for CNN using Vivado HLS

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

PandA-bambu public repository

Allo: A Programming Model for Composable Accelerator Design

A Compiler for the Popr Language

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

Time-sensitive affine types for predictable hardware generation

Polyphony is Python based High-Level Synthesis compiler.

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Tutorials on HLS Design