cpu-architecture

Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors

A textbook on understanding system on chip design

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.

VHDL , ModelSIM, Quartus, FPGA, Image Processing

The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture.

An analysis of intels goldmont plus uarch predecode caches core logic due to it being undocumented

An FPGA-based single-cycle RISC-V processor (RV32I) implemented in SystemVerilog. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. This project is ideal for learning computer architecture, digital design, and RISC-V ISA implementation.

Μια ενδεικτική υλοποίηση RISC-V επεξεργαστή και ενός υποστηρικτικού Assembler - Διπλωματική εργασία στο Τμήμα Μηχανικών Η/Υ και Πληροφορικής, Πανεπιστήμιο Πατρών / An Indicative RISC-V CPU Implementation and an Accompanying Assembler - Master's Diploma Thesis at the Computer Engineering and Informatics Department (CEID), University of Patras

Assembler, ISA & everything else featuring the 16-Bit Minecraft Redstone CPU "Frostybte"

A Verilog project for designing an Arithmetic Logic Unit (ALU) using pre-existing logic blocks. This ALU performs fundamental operations such as addition, subtraction, and logical shifts in a CPU architecture.

[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.

[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor

A study in MIPS microarchitecture trade-offs. This project implements three CPU designs: a single-cycle, a hardware-scheduled multicycle, and a software-scheduled pipelined core; then documents and contrasts their performance/complexity. Source is organized by variant (src_sc, src_hw, src_sw) with dedicated testbenches and write-ups.

Code snippets for the CpuFun blog

Tomasulo algorithm visualizer

General purpose processor with a RISC architecture and a five stage pipeline, implemented on a Cyclone IV FPGA using a development board

CPU Cache Simulation using gem5

This is a simple CPU emulator with custom architecture

16-bit CPU architecture implementation and verification using SystemVerilog