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suoto / hdl_checker

Repurposing existing HDL tools to help writing better code

vhdl xilinx Verilog systemverilog Python syntax-checker lsp-server Vim language-server questasim

Python

217

1 年前

Paebbels / JSON-for-VHDL

A JSON library implemented in VHDL.

vhdl JSON Parser fpga xilinx questasim Simulation synthesis

VHDL

3 年前

MJoergen / HyperRAM

Portable HyperRAM controller

xilinx artix fpga vhdl intel questasim

VHDL

8 个月前

Ghonimo / Pre_Silicon-AHB-to_APB-Verification

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

questasim Simulation systemverilog verification vip

SystemVerilog

1 年前

wyvernSemi / mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Verilog Simulation questasim verilator vhdl

VHDL

1 个月前

htminuslab / Modelsim-Unicorn

Modelsim QEMU Unicorn integration via the FLI

模拟器 questasim RISC-V vhdl

3 年前

NikLeberg / cosim_jtag

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

gdb vhdl questasim

10 天前

MJoergen / Avalon

Utilities for Avalon Memory Map

fpga intel xilinx questasim memory

VHDL

1 年前

Paebbels / pyIPCMI

A Python-based IP Core Management Infrastructure.

Python vhdl xilinx intel questasim synthesis Simulation infrastructure 数据库

Python

4 年前

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

questasim rtl rtl-design Verilog Finite-state machine synthesis systemverilog

Verilog

1 年前

Noamv7 / Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

systemverilog verification Verilog matrix-multiplication questasim

Verilog

1 年前

dave2pi / SublimeLinter-contrib-vlog

SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog

sublimelinter questasim Verilog systemverilog

Python

8 年前

yuravg / eda-scripts

Collection of scripts for EDA tools

fpga questasim

Shell

2 个月前

edaa-org / pyEDAA.ToolSetup

eda gtkwave Python questasim

Python

7 天前

angrammenos97 / imc

In-Memory Accelerator Controller

controller edge-computing Verilog questasim RISC-V systemverilog

SystemVerilog

1 年前

yuravg / color_questasim

A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

questasim Perl

Perl

9 个月前

Abdelrahman1810 / RTL-Verification-of-AMBA3_4-APB-Protocol

This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.

questasim systemverilog tcl Verilog

SystemVerilog

1 年前

teekamkhandelwal / SRAM_Controller

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

memory questasim Verilog memory-management

Verilog

10 个月前