questasim

Repurposing existing HDL tools to help writing better code

A JSON library implemented in VHDL.

Portable HyperRAM controller

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Modelsim QEMU Unicorn integration via the FLI

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

Utilities for Avalon Memory Map

A Python-based IP Core Management Infrastructure.

SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog

Collection of scripts for EDA tools

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

In-Memory Accelerator Controller

This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

Попытка написать несколько примеров кода на языке SystemVerilog.

Latest addition to REPO : Folder with vending machine design and TB including code coverage report