systemverilog-hdl

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

VUnit is a unit testing framework for VHDL/SystemVerilog

A Framework for Design and Verification of Image Processing Applications using UVM

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

A SystemVerilog source file pickler.

Simple single-port AXI memory interface

A simple UVM example with DPI

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

Contains commonly used UVM components (agents, environments and tests).

A Tcl-Library for scripted HDL generation

An FPGA design for simulating biological neurons

UVM

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

A simple UVM testbench using UVM Connect and Octave

Spring 2025 ecen4243 Computer Architecture Lab Material

Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)

Application Specific Integrated Circuit(ASIC)

Final Project third-perspective-shooting video game PokeHead and some other lab codes and design of ECE385 Digital Systems Laboratory

RISC-V processor co-simulation using SystemVerilog HDL and UVM.